_______________general description the max3691 serializer is ideal for converting 4-bit- wide, 155mbps parallel data to 622mbps serial data in atm and sdh/sonet applications. operating from a single +3.3v supply, this device accepts low-voltage differential-signal (lvds) clock and data inputs for interfacing with high-speed digital circuitry, and deliv- ers a 3.3v pecl serial-data output. a fully integrated pll synthesizes an internal 622mbps serial clock from a 155.52mhz reference clock. the max3691 is available in the extended-industrial temperature range (-40? to +85?), in a 32-pin tqfp package. ________________________applications 622mbps sdh/sonet transmission systems 622mbps atm/sonet access nodes add/drop multiplexers digital cross connects ____________________________features ? single +3.3v supply ? 155mbps parallel to 622mbps serial conversion ? 215mw power ? lvds parallel clock and data inputs ? differential 3.3v pecl serial-data output max3691 +3.3v, 622mbps, sdh/sonet 4:1 serializer with clock synthesis and lvds inputs ________________________________________________________________ maxim integrated products 1 max3691 max3668 sd- pclko- pclko+ lvds crystal reference pclki- pclki+ rclk- 0.1? 0.1? v cc gnd sd+ fil- fil+ 130 ? 130 ? 82 ? 1.5k 100pf 24.9k 82 ? v cc = +3.3v v cc = +3.3v v cc = +3.3v overhead generation pd3- pd3+ pd2- pd2+ pd1- pd1+ pd0- pd0+ this symbol represents a transmission line of characteristic impedance (z 0 = 50 ? ) rclk+ ___________________________________________________typical operating circuit 19-1207; rev 1; 7/04 part max3691ecj -40? to +85? temp range pin-package 32 tqfp ______________ordering information pin configuration appears at end of data sheet. evaluation kit available max3691ecj+ -40? to +85? 32 tqfp + denotes lead-free package. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max3691 +3.3v, 622mbps, sdh/sonet 4:1 serializer with clock synthesis and lvds inputs 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, differential lvds loads = 100 ? ?%, pecl loads = 50 ? ?% to (v cc - 2v), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. terminal voltage (with respect to gnd) v cc .........................................................................-0.5v to 5v all inputs.................................................-0.5v to (v cc + 0.5v) output current lvds outputs (pclko?................................................10ma pecl outputs (sd?.......................................................50ma continuous power dissipation (t a = +85?) tqfp (derate 10.20mw/? above +85?) ...................663mw operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .................................+300? t a = +25? to +85? pecl outputs unterminated t a = +25? to +85? differential input voltage = 100mv common-mode voltage = 50mv conditions v v cc - 1.03 v cc - 0.88 v oh output high voltage ma 38 65 100 i cc supply current v 0.925 v ol output low voltage v 1.475 v oh output high voltage ? 85 100 115 r in differential input resistance mv 70 v hyst threshold hysteresis v v cc - 1.81 v cc - 1.62 v ol output low voltage v 0 2.4 v i input voltage range mv -100 100 v idth differential input threshold units min typ max symbol parameter % ? ?0 ? r o change in magnitude of single-ended output resistance for complementary states ? 40 70 140 r o single-ended output resistance mv 25 ? v os change in magnitude of output offset voltage for complementary states mv 250 400 v od differential output voltage mv 25 ? v od change in magnitude of differential output voltage for complementary states t a = +25? v 1.125 1.275 v os output offset voltage pecl outputs (sd) lvds inputs and outputs (pclki, rclk, pclko, pd_) t a = -40? v cc - 1.08 v cc - 0.88 t a = -40? v cc - 1.95 v cc - 1.62
max3691 +3.3v, 622mbps, sdh/sonet 4:1 serializer with clock synthesis and lvds inputs _______________________________________________________________________________________ 3 note 1: ac characteristics guaranteed by design and characterization. note 2: assumes a 50% duty cycle ?%. t a = -40? to +85? (note 2) conditions ps 600 t h parallel data-hold time ps 200 t su mhz 622.08 f sclk serial clock rate parallel data-setup time ns -0.7 +3.3 t skew pclko to pclki skew ps rms 13 0 output jitter ps 400 t r, t f pecl differential output rise/fall time units min typ max symbol parameter ac electrical characteristics (v cc = +3.0v to +3.6v, differential lvds load = 100 ? ?%, pecl loads = 50 ? ?% to (v cc - 2v) t a = +25?, unless otherwise noted. typical values are at v cc = +3.3v.) (note 1) 100 0 -50 -25 25 100 supply current vs. temperature 20 60 80 max3691-01 temperature (?) supply current (ma) 050 40 75 -20 -120 -50 -25 25 100 parallel data-setup time vs. temperature -100 -60 -40 max3691-02 temperature (?) parallel data-setup time (ps) 050 -80 75 250 150 -50 -25 25 100 parallel data-hold time vs. temperature 170 210 230 max3691-03 temperature (?) parallel data-hold time (ps) 050 190 75 __________________________________________typical operating characteristics (v cc = +3.0v to +3.6v, differential lvds loads = 100 ? , unless otherwise noted.)
max3691 +3.3v, 622mbps, sdh/sonet 4:1 serializer with clock synthesis and lvds inputs 4 _______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (v cc = +3.0v to +3.6v, differential lvds loads = 100 ? , unless otherwise noted.) 6 -4 -50 -25 25 100 pclko-to-pclki skew vs. temperature -2 2 4 max3691-04 temperature (?) pclko-to-pclki skew (ns) 050 0 75 1.21v 0.59v 161ps/div serial-data output eye diagram (622mbps, 2 7 -1 prbs) 62mv/ div max3691-05 oc-12 sonet mask 908mv 808mv 10ps/div serial-data output jitter 10mv/ div max3691-06 f rclk = 155.52mhz mean 23.88ns rms ? 8.418ps pkpk 70.2ps ? 68.774% ? 95.534% ? 99.738% ______________________________________________________________pin description name function 1, 3, 5, 7 pd0+ to pd3+ noninverting lvds parallel data inputs. data is clocked in on the pclki signal? positive transition. 2, 4, 6, 8 pd0- to pd3- inverting lvds parallel data inputs. data is clocked in on the pclki signal? positive transition. pin 9, 17, 18, 19, 24, 25, 32 gnd ground 10 pclko- inverting lvds parallel-clock output. use pclko to clock the overhead management circuit. 15 sd+ noninverting pecl serial-data output 14 sd- inverting pecl serial-data output 12, 13, 16, 20, 21, 28, 29 v cc +3.3v supply voltage 11 pclko+ noninverting lvds parallel-clock output. use pclko to clock the overhead management circuit. 23 fil+ filter capacitor input. see typical operating circuit for external-component connections. 22 fil- filter capacitor input. see typical operating circuit for external-component connections. 26 rclk+ noninverting lvds reference clock input. connect (ac couple) a crystal reference clock (155.52mhz) to the rclk inputs. 30 pclki+ noninverting lvds parallel clock input. connect the incoming parallel-data-clock signal to the pclki inputs. note that data is updated on the positive transition of the pclki signal. 27 rclk- inverting lvds reference clock input. connect (ac couple) a crystal reference clock (155.52mhz) to the rclk inputs. 31 pclki- inverting lvds parallel clock input. connect the incoming parallel-data-clock signal to the pclki inputs. note that data is updated on the positive transition of the pclki signal.
max3691 +3.3v, 622mbps, sdh/sonet 4:1 serializer with clock synthesis and lvds inputs _______________________________________________________________________________________ 5 _______________detailed description the max3691 serializer comprises a 4-bit parallel input register, a 4-bit shift register, control and timing logic, a pecl output buffer, lvds input/output buffers, and a frequency-synthesizing pll (consisting of a phase/ frequency detector, loop filter/amplifier, and voltage- controlled oscillator). this device converts 4-bit-wide, 155mbps data to 622mbps serial data (figure 1). the pll synthesizes an internal 622mbps reference used to clock the output shift register. this clock is generated by locking onto the external 155.52mhz reference-clock signal (rclk). the incoming parallel data is clocked into the max3691 on the rising transition of the parallel-clock- input signal (pclki). the control and timing logic ensure proper operation if the parallel-input register is latched within a window of time that is defined with respect to the parallel-clock-output signal (pclko). pclko is the synthesized 622mbps internal serial- clock signal divided by four. the allowable pclko-to- pclki skew is -0.7ns to +3.3ns. this defines a timing window at about the pclko rising edge, during which a pclki rising edge may occur. figure 2 is the timing diagram. max3691 pd3+ pd3- 4-bit parallel input register phase/freq detect control 4-bit shift register lvds lvds pclki- pclki+ rclk- rclk+ fil+ fil- pclko+ pclko- vco pecl sd+ sd- shift latch lvds pd2+ pd2- lvds pd1+ pd1- lvds pd0+ pd0- lvds lvds figure 1. functional diagram
max3691 low-voltage differential-signal (lvds) inputs and outputs the max3691 features lvds inputs and outputs for interfacing with high-speed digital circuitry. the lvds standard is based on the ieee 1596.3 lvds specifi- cation. this technology uses 250mv?00mv differen- tial low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immu- nity. for proper operation, the parallel-clock lvds outputs (pclko+, pclko-) require 100 ? differential dc termi- nation between the inverting and noninverting outputs. do not terminate these outputs to ground. the parallel data and parallel clock lvds inputs (pd_+, pd_-, pclki+, pclki-) are internally terminated with 100 ? differential input resistance, and therefore do not require external termination. pecl outputs the serial-data pecl outputs (sd+, sd-) require 50 ? dc termination to (v cc - 2v). see the alternative pecl- output termination section. +3.3v, 622mbps, sdh/sonet 4:1 serializer with clock synthesis and lvds inputs 6 _______________________________________________________________________________________ t skew sd note: signals shown are differential. for example, pclko = (pclko+) - (pclko-). *pd3 = d3; pd2 = d2; pd1 = d1; pd0 = d0. d0 d1 d2 d3 pd_ valid parallel data* pclki pclko t su t h figure 2. timing diagram
___________________chip information transistor count: 1633 max3691 +3.3v, 622mbps, sdh/sonet 4:1 serializer with clock synthesis and lvds inputs _______________________________________________________________________________________ 7 max3691 sd+ sd- v cc - 2v 50 ? 50 ? z 0 = 50 ? high- impedence inputs z 0 = 50 ? max3691 sd+ sd- +3.3v 130 ? 130 ? 82 ? 82 ? z 0 = 50 ? pecl inputs z 0 = 50 ? figure 3. alternative pecl-output termination tqfp top view fil+ fil- v cc v cc gnd gnd gnd gnd pd0- pd1+ pd1- pd2+ pd2- pd0+ pd3- pd3+ sd+ sd- pclko- v cc v cc pclko+ v cc gnd rclk+ rclk- pclki- v cc v cc pclki+ gnd gnd 32 31 30 29 28 27 26 25 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 max3691 __________________pin configuration __________applications information alternative pecl-output termination figure 3 shows alternative pecl output-termination methods. use thevenin-equivalent termination when a (v cc - 2v) termination voltage is not available. if ac coupling is necessary, be sure that the coupling capac- itor is placed following the 50 ? or thevenin-equivalent dc termination. layout techniques for best performance, use good high-frequency layout techniques. filter voltage supplies and keep ground connections short. use multiple vias where possible. also, use controlled-impedance transmission lines to interface with the max3691 clock and data inputs and outputs.
max3691 +3.3v, 622mbps, sdh/sonet 4:1 serializer with clock synthesis and lvds inputs tqfppo.eps e 1 2 21-0054 package outline, 32/48l tqfp, 7x7x1.4mm e 2 2 21-0054 package outline, 32/48l tqfp, 7x7x1.4mm maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
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